This invention relates to a transistor device and more particularly, to a MOS transistor device and a method for making such a device.
As semiconductor devices are highly integrated, the fineness in the dimensional ruling of the semiconductor manufacturing processes has become a problem. In fact, in element isolation techniques, the conventional LOCOS method cannot cope with the problem of the fineness with the influence of the birds beak. Hence, attention has been paid to SOI (semiconductor on insulator) techniques for element isolation in semiconductor devices of the 0.1 .mu.m ruling type. The transistor devices made by use of the SOI technique are highly resistant to .alpha. rays. Moreover, the above semiconductor device does not produce any parasitic capacitance between the source-drain region and the semiconductor substrate as will be undesirably involved in a transistor device which is made using a bulk semiconductor substrate, so that the high working speed of the transistor device is insured. Thus, with the transistor device using the SOI technique, high reliability and high working speed can be attained.
Reference is now made to FIGS. 1A to 1F, with which a method of making a MOS transistor using the known SOI technique is described.
[Step-10]
Initially, a first semiconductor substrate 10 made of silicon is provided, and grooves 20 are formed on one side 10A of the substrate 10 (FIG. 1A).
[Step-20]
Then, an insulating layer 21 made of silicon dioxide is deposited in the grooves 20 and on the one side 10A of the first semiconductor substrate 10. Thereafter, a polysilicon layer 22 is further deposited on the insulating layer 21, followed by smoothing the surface of the polysilicon layer 22 (FIG. 1B).
[Step-30]
Subsequently, the polysilicon layer 22 formed on one side 10A of the first semiconductor substrate 10 and a second semiconductor substrate 11 made of silicon are bonded together (FIG. 1C).
[Step-40]
The first semiconductor substrate 10 is polished at the other side 10B thereof until the grooves 20 are exposed at respective bottoms 20A thereof (FIG. 1D). By this, a semiconductor layer 30 made of silicon is exposed between the adjacent grooves 20. The respective semiconductor layers 30 are electrically isolated with the grooves 20 and the insulating layers 21. It will be noted that the semiconductor layers 30 are formed of the first semiconductor substrate 10.
[Step-50]
Then, a gate electrode region 41, gate side walls 44, a channel region 45, a source region 46 and a drain region 47 are formed on the semiconductor layer 30 according to any known procedure (FIG. 1E). In this manner, a MOS transistor is made. Next, a layer insulating layer 60 is formed entirely thereover, after which openings 61 are respectively formed at regions corresponding to the source region 46 and the drain region 47 (FIG. 1F), thereby forming contact holes.
As the MOS transistor having an SOI structure is made finer, it is necessary to make the semiconductor layer 30 smaller in thickness. If the semiconductor layer 30 is not made thinner according to the fineness of the dimensional rule, there arise the problem of degradation of the breakdown voltage between the source and drain regions and the problem on the short channel effect.
With the MOS transistor having an SOI structure, the source region 46, channel region 45 and drain region 47 are formed on the insulating layer 21. Therefore, when the transistor device is in a pinch-off state where holes or electrons move through the semiconductor layer 30, the high electric field is accelerated at the end of the drain region, so that holes or electrons are impact-ionized, thereby generating electron-hole pairs. Either of the thus generated electrons or holes are accumulated in the semiconductor layer 30 (particularly, in the channel region 45). This eventually lowers the breakdown voltage between the source and drain regions. It will be noted that with ordinary MOS transistors, a well is grounded through the semiconductor substrate, so that such problems as set out above are not produced at all.
One of the attempts for solving the above problem is a technique wherein a silicide layer is formed on the surface of the source and drain regions and carriers accumulated in the channel region are grounded through the silicide layer as set out, for example, in "Suppression of Latch in SOI MOSFETs by Silicidation of Source", L. J. McDAID, et al., Electronics Letters, 23rd May 1991, vol. 27, No. 11, pp. 1003-1005. The carriers accumulated in the channel region are not completely grounded, and an improvement in the breakdown voltage between the source and drain regions is not satisfactory.
With the dimensional ruling of 0.5 .mu.m, it has been generally accepted that the required thickness of the semiconductor layer 30 is 100 nm. With the dimensional ruling of 0.35 .mu.m, the required thickness of the semiconductor layer 30 is about 70 nm. As the thickness of the semiconductor layer 30 is made smaller in this way, there arises the problem that the sheet resistances of the source region 46 and the drain region 47 increase. For instance, when the thickness of the semiconductor layer 30 is about 100 nm, the sheet resistance is approximately 70.OMEGA./.quadrature.. When the thickness of the semiconductor layer 30 is about 70 nm, the sheet resistance increase up to not-lower than 100.OMEGA./.quadrature.. The thickness of the semiconductor layer 30 will further become thinner in the future, with the attendant problem that the sheet resistance of the source 46 and the drain 47 increases more and more. By the increase of the sheet resistance, the parasitic resistance of the transistor device increases, resulting in the degradation of the device characteristics.
On the other hand, when the semiconductor layer 30 is made thinner, the semiconductor layer 30 may be fully lost by 1aover-etching on formation of the openings 61 through anisotropic dry etching of the insulating layer. In addition, there is another problem that the area of contact between the contact hole and the semiconductor layer 30 is lessened, thereby increasing the contact resistance.
Moreover, when the semiconductor layer 30 is made thin, the peak of the electric field at the drain region becomes high. For the transistor devices having an SOI structure, this results in degradation of the device and also in characteristic degradation, such as of a parasitic bipolar effect.